1. Field of the Invention
The present invention relates to a semiconductor device that uses a charge pump circuit to generate a write voltage for a memory cell.
2. Description of Related Art
In a flash memory and an EEPROM (Electrically Erasable and Programmable ROM), a write voltage VPP which is higher than a power source voltage VDD is generally required for data writing. There is known a semiconductor device which generates such a high write voltage VPP by using a charge pump circuit. However, if boosting by the charge pump circuit is insufficient, a desired write voltage VPP is not obtained, which may cause a data write error.
U.S. Pat. No. 7,187,600 discloses a technique that generates the write voltage VPP from the power source voltage VDD by using a charge pump circuit and performs data programming/erasing for a nonvolatile memory by using the write voltage VPP. At this time, a low voltage detection circuit checks the power source voltage VDD itself that is input to a chip. If the power source voltage VDD is less than a predetermined value, a control resistor disables the charge pump circuit.
Japanese Patent Publication JP-2000-353392A discloses a technique that monitors a charge pump output (write voltage VPP) in order to suppress a data write error. FIG. 1 shows a configuration of a semiconductor device disclosed in Japanese Patent Publication JP-2000-353392A.
At a time of data writing, a write start signal ENA is activated. In response to that, a write control circuit 10 activates an oscillation instructing signal START. In response to the oscillation instructing signal START, an oscillation circuit 20 generates clock signals CK and CK/ and output the clock signals CK and CK/ to a charge pump circuit 30. The charge pump circuit 30 operates based on the clock signals CK and CK/ to generate the write voltage VPP. A memory circuit 40 uses the write voltage VPP to write a data to a memory cell.
Here, a high voltage detection unit 50 monitors whether or not the write voltage VPP is increased to a desired voltage value. More specifically, the write control circuit 10 outputs a period setting signal TEST of one pulse along with activating the oscillation instructing signal START. The period setting signal TEST is used for setting a test period during which the write voltage VPP is monitored. During the test period when the period setting signal TEST is at the High level, a switch in the memory circuit 40 cuts off supply of the write voltage VPP to a memory cell, while the high voltage detection unit 50 compares the write voltage VPP with a predetermined reference voltage.
In a case where the write voltage VPP at a time of the end of the test period does not reach the predetermined reference voltage, the high voltage detection unit 50 outputs a determination signal LVPP indicating an error and also outputs a disable signal DIS/ for stopping the boosting operation to the write control circuit 10. If the disable signal DIS/ is activated, the write control circuit 10 deactivates the oscillation instructing signal START, and thereby the oscillation circuit 20 and the charge pump circuit 30 stop operating.
As described above, if the write voltage VPP does not reach the predetermined value at the time of the end of the test period, the determination signal LVPP indicating an error is output to the outside. Furthermore, the operation of the charge pump circuit 30 is stopped and thereby the write voltage VPP is decreased. Therefore, even if the write voltage VPP is applied to the memory cell, it does not affect data stored in the memory cell. That is, uncertain data writing and erroneous data rewriting can be prevented.